1. Field of the Invention
The present invention relates to a microprogram transfer register designation system for use in a microprogram controlled microprocessor having a plurality of internal buses, and, the present invention relates more specifically to a microprogram transfer register designation system for designating, by one transfer register code, one set of source registers and destination registers which are respectively of the same number as that of the internal buses.
2. Description of Related Art
At present, the control for internal hardware resources in microprocessors are mainly of a so-called microprogram control system. This system includes a read only memory (ROM) provided internally in the microprocessor for storing a microprogram composed of a sequence of control codes (called "microcodes") and a microprogram sequencer for sequentially reading and decoding the microcodes from the ROM for each one word so as to control various hardware resources in the microprocessors. The internal hardware resources in the microprocessor includes various arithmetic logic units and registers, and each microprogram instructs various operations such as interregister data transfer, logic operations, condition decisions, branches, etc., similarly to machine languages for computers.
In the microprogram, execution speed is preferred over generality and descriptivity of programs, and therefore, each instruction has as many functions as possible which can be executed in parallel, such as a transfer instruction, an arithmetic operation instruction, a conditional branch and the like so that a parallel operation will be realized to the maximum extent, and therefore the hardware resources are efficiently utilized. In this aspect, the microprogram is different from the machine language for general computers. Accordingly, ordinary microcodes have a plurality of fields in one instruction so that different functions are described independently of one another.
In the case of microprocessors having only one internal data bus, the microcodes are not so long and therefore, the microprogram control is very effective. However, in the case of microprocessors having two or more internal data buses, the microcodes need a field of a long word length for designating the source registers and the destination registers for data transfers made by using the respective internal data buses.
Conventionally, in order to shorten the field for the interregister transfer, there has been proposed to previously prepare some number of source register sets each designating one source register for each of the internal buses and some number of destination register sets each designating one destination register for each of the internal buses. In this manner, all possible combinations of source registers and destination registers cannot be prepared because the preparation for all possible combinations needs a very long field for designating the source register set and the destination register set. Therefore, the data transfer between a set of registers which is not included in the previously prepared combinations must be executed by sequentially executing the data transfers between two or more sets of registers which are included in the previously prepared combinations. This is disadvantageous in that the content of an unintended register is destroyed. In order to avoid the destruction of the data, the microprogram inevitably becomes more complicated.